1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to an improvement in an insulated gate bipolar transistor (hereinafter referred to as IGBT), for preventing a latch-up phenomenon.
2. Description of the Prior Art
FIG. 1 is a sectional view schematically showing the structure of a conventional IGBT device. In general, an IGBT device 1 is formed by a number of IGBT elements 2 connected in parallel with each other. FIG. 2 shows an equivalent circuit of a single IGBT element 2, and FIG. 3 shows an equivalent circuit of the entire IGBT device 1.
Referring to FIG. 1, an N.sup.- -type layer 4 is epitaxially grown on one major surface of a P.sup.+ -type semiconductor substrate 3. Impurities are selectively diffused from the surface of the N.sup.- -type layer 4 to form a plurality of P-type regions 5, while impurities are selectively diffused from the surface of each P-type region 5 to form a pair of N.sup.+ -type regions 6. An insulation film 7 is formed on the surfaces of the P-type regions 5 between the surface of the N.sup.- -type layer 4 and those of the N.sup.+ -type regions 6. The insulation film 7 also covers the surface of the N.sup.- -type layer 4 to be integral between each adjacent pair of IGBT elements 2. A gate electrode 8 of, e.g., polysilicon is formed on the insulation film 7, while emitter electrodes 9 of metal such as aluminum are formed to be electrically connected to both of the P-type regions 5 and N.sup.+ -type regions 6. Each emitter electrode 9 is commonly provided between each adjacent pair of IGBT elements 2 in the same P-type region 5. The gate electrode 8 and the emitter electrodes 9 are in multilayer structure through insulation films (not shown), to be commonly electrically connected to a number of IGBT elements 2. On the rear surface of the P.sup.+ -type semiconductor substrate 3, a metal collector electrode 10 is integrally provided for all of the IGBT elements 2. The gate electrode 8 is connected to a gate terminal G of the IGBT device 1 and each emitter electrode 9 is connected to an emitter terminal E, while the collector electrode 10 is connected to a collector terminal C through wire bonding and die bonding respectively.
Thus, each IGBT element 2 forms an N-channel double diffusion vertical MOS-FET on the P.sup.+ -type semiconductor substrate 3, which may be regarded as a composite element of a pnpn thyristor and an N-channel MOS-FET, as obvious from the equivalent circuit shown in FIG. 2. When positive voltage is applied to the collector terminal C and the emitter terminal E is grounded while appropriate control voltage is applied to the gate terminal G in normal operation, holes are injected in a drain formed by the N.sup.- -type layer 4, thereby to achive low on-resistance. No current flows in the gate electrode 8 since the same is isolated from an active region of the transistor. In other words, the IGBT device 1 has both characteristics of low on-resistance of a bipolar transistor and high input impedance of a MOS-FET. Thus, the IGBT device 1 can be formed by several thousands of parallely connected IGBT elements 2, for example, thereby to implement a power transistor of high performance which can supply current of about 50 A.
When small current flows in the IGBT element 2, potential difference across a diffusion resistor R.sub.S of the P-type region 5 is small and a shorted state is maintained between the base and the emitter of an npn transistor 11. The npn transistor 11 is not driven in this state, and the IGBT element 2 operates as a composite element of an N-channel MOS-FET 12 and a pnp transistor 13. The base current of the pnp transistor 13 is controlled by the N-channel MOS-FET 12 in in this case, whereby main current i.sub.c for the IGBT element 2 can be controlled by a control signal applied to the gate terminal G.
As obvious from the equivalent circuit of FIG. 2, the main current i.sub.c for the IGBT element 2 is the sum of electron current i.sub.e flowing in the MOS-FET 12 and collector current (hole current) i.sub.h of the pnp transistor 13. Assuming that symbol i.sub.E represents current flowing in the emitter terminal E, the following relation holds: EQU i.sub.C =i.sub.E =i.sub.e +i.sub.h ( 1)
With reference to FIG. 1, a channel is formed in the P-type region 5 by the control signal applied to the gate electrode 8, whereby electrons are injected in the drain, i.e., the N.sup.- -type region 4 while holes are injected in the base of the pnp transitor 13, i.e., the N.sup.- -type region 4 from the collector, i.e., the P.sup.+ -type region 3, so that the injected holes are partially recombined with the electrons to be extinguished while the remaining holes flow in the P-type region 5 as the collector current i.sub.h.
The conventional IGBT device 1 is in the aforementioned structure, and when the main current i.sub.c for the IGBT element 2 is increased by some external cause such as noise applied to the gate terminal G, the electron current i.sub.e and the hole current i.sub.h are increased. If the hole curent i.sub.h exceeds a prescribed level at this time, the voltage drop across the resistor R.sub.S exceeds a threshold value for conduction of the npn transistor 11. In other words, the base-emitter junction of the npn transistor 11 is forward-biased to exceed the diffusion potential, whereby the pnpn thyristor formed by the npn transistor 11 and the pnp transistor 13 enters a conducting state. In this state, the main current i.sub.c for the IGBT element 2 cannot be controlled by the control signal applied to the gate terminal G. This is the so-called latch-up phenomenon. The P-type region 5 may be formed so that the resistance R.sub.S is reduced to the minimum in order to prevent the latch-up phenomenon, whereas such reduction is restricted. Therefore, when the latch-up phenomenon takes place, excess main current i.sub.c incontrollably flows to break the IGBT device 1 as well as to damage peripheral devices connected to the same.